1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) having a sub-amplifier configuration.
2. Description of the Background Art
A conventional semiconductor memory device disclosed in FIG. 10 of Japanese Patent Laying-Open No. 6-187782 includes a plurality of memory cell arrays, and an auxiliary read amplifier provided for each of the plurality of sense amplifiers in each memory cell array, and connected to each sense amplifier and a pair of sub-input/output line. The source of a transistor within the auxiliary read amplifier is connected to the source of a transistor in each sense amplifier.
The conventional semiconductor memory device with such a configuration, however, requires a precharge circuit for equalizing the sub-input/output line to the source voltage of the transistor within the sense amplifier. Accordingly, the conventional semiconductor memory device requires an extra circuit area for the precharge circuit. Consequently, the circuit area for the entire semiconductor memory device increases.